Abstract
Embedding of Asynchronous Wave
Pipelines into Synchronous Data Processing.
Brief description
This paper will make a step forward
for a wider usability of asynchronous wavepipelines. Since the synchronous
approach of pipelining is so popular, it is obvious to take a nearer look
at the interface between two circuits of their respective circuit style.
Asynchronous wave pipelines are to be classified as in between synchronous
and asynchronous architectures, so our subject is to replace for performance
reasons one or more combinatorial blocks of a synchronous pipeline with
an asynchronous wave pipeline. To do such a substitution, additional circuits
are presented for interfacing between static and pulsed signals, generating
the request pulse which accompanies a data wave, and for synchronisation
with the clock signal which latches in the results. Switching from static
to pulsed signals and vice versa is necessary if the synchronous pipeline
deals with static signals whereas asynchronous wavepipelines use self-resetting
CMOS (SRCMOS) and therefore deal with pulsed data. The request pulse is
derived from the clock of the input register in such a way that it accompanies
the data waves created out of the correct static data. As a data wave and
request pulse propagates out of the AWP, they are asynchronous to the clock
of the output register and additionally they are not static. The proposed
circuits to do these jobs are analysed with regard to power consumption
and latency. First simulations demonstrates that replacing a combinatorial
block of a synchronous pipeline with clock frequencies of up to 1.5 GHz
in 0.35um CMOS is feasible.
| Updated on 2002/05/13 by Stephan
Hermanns. |