Because of the growing importance and increasing complexity of embedded systems, it is highly desired to shift the design process to a higher level of abstraction and to support an early system validation. Based on an abstract specification denoted as extended Task Graph (eTG) and alloca-tion, binding, and scheduling information, a scheduled and executable SystemC model is gener-ated, which represents a transaction level model (TLM) of the distributed embedded system. The well-defined specification model and its execution semantic allow the clear separation of commu-nication and core functionality. Therewith, the whole communication and run-time control can be automatically generated, and the SystemC simulation kernel enables an early execution and timing validation of the specification. The implementation of the associated control units is based on finite state machines, which are responsible for the run-time control including communication and execu-tion order. By adding the core functionality of the tasks to the model and by refining the hardware and software parts, complete and synthesizeable models are generated. A further benefit of the pro-posed specification model is the consistent definition of interfaces, which support the encapsulation of blocks and enable the reuse of IP cores, thus leading to a hierarchical specification of distributed embedded systems.