Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach

Published in: Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004) with the 3rd International Conference on Embedded Systems, ISBN 0-7695-2072-3, January 2004

Abstract

The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application and limitations of the architecture. In a top-down approach a real-time MPEG 1 Layer 3 (MP3) decoder is designed on this SoC, which integrates FPGA resources and an AVR microcontroller core within a single chip. An intensive design space exploration based on simulations on different levels of abstractions is fundamental for a real-time implementation on this limited architecture. After determining a suited functional partitioning a special DSP is implemented on the FPGA, wherefore an instruction set simulator is build, which allows concurrent HW/SW development.

Authors

Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger

Download

Article (PDF) -- © 2004 IEEE Computer Society